1. Field of the Invention
The present invention generally relates to an integration type digital-to-analogue converter (hereinafter also referred to simply as D/A converter) incorporating current supply sources. More particularly, the invention concerns a D/A converter suited for use in a digital-recorded-signal reproducing apparatus having a wide dynamic range for reproducing a signal recorded in a digital form.
2. Description of the Prior Art
In recent years, there are available on the market the apparatuses for recording and/or reproducing audio signals on a digital basis such as digital audio disk players typified by compact disk players (CD players), digital audio tape players (DAT players) and the like.
FIG. 1 of the accompanying drawings shows in a block diagram a typical one of the hitherto known digitally-recorded-signal reproducing apparatus for reproducing a signal recorded in a digital form in the system mentioned above. Referring to FIG. 1, a reference numeral 101 denotes a recording medium for recording signal optically or magnetically (i.e. with the aid of optical or magnetic writing means), a numeral 102 denotes a reproducing or pickup head for reading optically or magnetically the signal recorded on the recording medium 101, a numeral 103 denotes a reproduction amplifier for performing equalization of waveform of electric signal produced by the reproducing head 102 as wall as data-strobe processing in preparation for conversion to digital codes and the like processing, a numeral 104 denotes a digital signal processing circuit for performing deinterleaving, error detection/correction and the like processings, a numeral 105 denotes a current source circuit for digital/analogue (D/A) conversion which supplies a constant current for a time period corresponding to the value of the digital signal produced by the digital signal processing circuit 104, a numeral 106 denotes an integrator for integrating the output current of the current source 105, a numeral 107 denotes a re-sample circuit for sampling the analogue output of the integrator 106 at an appropriate timing after the analogue output has attained an analogue voltage corresponding to the input digital value, a numeral 108 denotes a low-pass filter (or LPF) for eliminating spurious signals possibly making appearance at the sampling period of the re-sample circuit, and finally a reference numeral 109 denotes an output terminal for the reproduced analogue signal representative of the recorded information or data.
Now, description will be focussed on the integration type digital-to-analogue or D/A converter which is constituted by the current source 105 for D/A conversion and integrator 106.
Generally, the integration type D/A converter is so arranged as to integrate the constant current supplied from the current source 105 for a time period determined in dependence on the digital input signal to thereby produce a corresponding analogue output signal.
An arrangement of the integration type D/A converter is shown in a functional block diagram in FIG. 2. A similar arrangement of such D/A converter is disclosed in Japanese Patent Application Publication No. 4116/63. Referring to FIG. 2, a numeral 1 denotes an input terminal for a digital signal, 2 denotes an input terminal for a clock signal, 3 denotes a counter, and 4 denotes a switch for interrupting and conducting a current supplied from a constant current source 5. A numeral 6 denotes a control circuit, 7 denotes an operational amplifier constituting a main part of the integrator, 8 denotes a capacitor, 9 denotes a reset switch for discharging electric charge stored in the capacitor 8, and 10 denotes an output terminal for the analogue output signal of the integrator.
In operation, the reset switch 9 is closed at first to allow the electric charge stored in the capacitor 8 to be discharged. Simultaneously, the digital data signal applied to the input terminal 1 is loaded in the counter 3. Thereafter, the counter 3 is operated in response to the clock signal applied to the clock signal input terminal 2 to thereby cause the switch 4 to be closed for a period corresponding to the digital data loaded in the counter, whereby a current can flow to the capacitor 8 from the constant current source 5. In the mean time, the output voltage produced by the integrator composed of the operational amplifier 7 and the capacitor 8 and appeared at the output terminal 10 increases with a predetermined slope or ramp. Upon opening of the switch 4, the output voltage of the integrator is held at a level of a constant value. Through the operation briefed above, the D/A conversion is realized for obtaining the analogue output voltage corresponding to the input digital data value. In this conjunction, it is noted that the conversion time T can be given by the following expression: EQU T=2.sup.N .times.f.sub.clk
where N represents the bit number of the D/A converter and f.sub.clk represents the clock frequency applied to the counter 3. Accordingly, in order to realize the D/A converter whose bit number N is equal to 16 and whose conversion time is about 10 .mu.S, the following condition has to be satisfied. EQU f.sub.clk .apprxeq.6.6 GHz
The clock frequency of such a large value is difficult to realize in the present state of the integrated circuit technology. It should here be mentioned that with the phrase "conversion time T", it is intended to mean the time required for converting the digital signal of N bits each of which is, for example, logic "1" to a corresponding analogue (voltage) signal.
Another arrangement of the integration type D/A converter of 16 bits which permits the clock frequency of the counter under consideration to be decreased is shown in FIG. 3 of the accompanying drawings. A similar structure of this D/A converter is disclosed in an article entitled "16-Bit IC A-D, D-A converter of Low Distortion Factor for Digital Audio Applications" (Nikkei Electronics, Jan. 18, 1982, p.p. 193-203). Now referring to FIG. 3 in which parts functionally equivalent to those shown in FIG. 1 are denoted by like reference symbols, a numeral 11 denotes a constant current source provided for integration of the eight higher order bits of the input digital data, 12 denotes a constant current source provided for integration of the lower order eight bits, 13 denotes a switch for selectively intercepting and conducting a current from the constant current source 11 provided for the upper order eight bits, 14 denotes a switch for selectively intercepting and conducting a current from the constant current source 12 provided for the lower order eight bits, 15 denotes a counter for determining the period during which the switch 13 provided in connection with the integration of upper order bits eight is turned on, 16 denotes a counter for determining the period during which the switch 14 for integration of the lower order eight bits is closed, 17 denotes a control circuit for determining the timings at which the counters 15 and 16 and the switch 9 are controlled, 18 denotes an input terminal for the signal of digital data containing the upper order eight bits, 19 denotes an input terminal for the signal of digital data containing the lower order eight bits, and a numeral 20 denotes an input terminal for a clock signal.
FIG. 4 shows a timing diagram for illustrating operation of the integration type D/A converter shown in FIG. 3. In FIG. 4, a curve 21 represents waveform of the analogue output signal of the integrator, a numeral 22 designates the conducting period of the discharging or reset switch 9, a numeral 23 designates the conducting period of the switch 13 for the upper order eight bits, 24 designates the conducting period of the switch 14 for the lower order eight bits, and 25 designates the period in which the analogue signal resulting from the D/A conversion is outputted.
More specifically, in operation of the integration type D/A converter shown in FIG. 3, the switch 9 is closed at the beginning of the conducting period 22 to thereby discharge electric charge stored in the capacitor 8. At the same time, digital data of 16 bits is divided into upper and lower order bit strings each consisting of eight bits which are loaded in the counters 15 and 16 by way of the input terminals 18 and 19, respectively. Subsequently, the switches 13 and 14 are turned on (i.e. made conductive) for the periods corresponding to the data placed in the counters 15 and 16, respectively. The values of the constant currents supplied from the constant current sources 11 and 18 for the upper order eight bits and the lower order eight bits, respectively, are weighted at the ratio of 2.sup.8 to 1. During the current conducting periods 23 and 24 determined as the function of the data given by the upper order eight bits and the lower order eight bits, respectively, the capacitor 8 is charged with the currents supplied from the constant current sources 11 and 12, respectively, to thereby produce the waveform 21 at the analogue output 10 of the integrator. The analogue signal thus making appearance at the analogue output terminal 10 represents the analogue value resulting from the D/A conversion of the input digital data and is supplied to a succeeding stage during the output period 25.
By providing two constant current sources for upper order eight bits and lower order eight bits, respectively, of the digital data consisting of 16 bits and weighting the currents thereof at the ratio mentioned above, the clock frequency f'.sub.clk for the counters can be decreased to a practically realizable value as follows: ##EQU1##
However, in either of the integration type D/A converters shown in FIGS. 2 and 3, the voltage waveform of the signal at the output terminal 10 of the integrator includes only positive signal swings relative to the ground potential level to which the non-inverting input terminal of the operational amplifier 7 of the integrator is coupled, as will be seen in FIG. 4. In other words, swings or changes of output voltage signal of the integrator is confined within a range defined between the ground potential level and a certain positive value or level.
However, in consideration of the facts that the center level of the A.C. signals such as audio signal or the like in general is at the ground potential, that the source voltage of the operational amplifier contains two components which equal to each other in the absolute value but have opposite polarities, it is desirable that the output voltage signal of the integrator should swing or vary about the center level which is equal to the ground potential level. In this connection, it may readily occur that the above problem can be solved by setting the non-inverting input level of the operational amplifier 7 lower than the ground potential level. In that case, however, actual implementation of the circuit will encounter another problem in conjunction with the voltages required for operating or driving various circuit elements such as transistors or the like constituting the switches 4, 13 and 14 and the constant current sources 5, 11 and 12, rendering it difficult in practice to lower the non-inverting input level of the operational amplifier 7 of the integrator than the ground potential level.
For this reason, the circuit arrangement disclosed in the article "16-Bit IC A-D, D-A Converter of Low Distortion Factor for Digital Audio Application" cited hereinbefore is made such that the audio signal produced at the output of the integrator is taken out as a voltage signal varying or swinging within a range between the ground potential level and given positive level and subsequently added with an offset voltage so that the ground potential level constitutes the center level of the audio signal.
In the case of the arrangement mentioned above, however, performance or processing capability of the operational amplifier constituting the integrator can not be utilized effectively and fully. More specifically, since the output signal of the integrator finds itself only in the positive voltage region, the output voltage of the operational amplifier is reduced to a half of the maximum voltage which can pass through the operational amplifier. In other words, the dynamic range of the analogue signal produced by the D/A converter is undesirably narrowed to a serious disadvantage.
As an attempt to mitigate the reduction of the dynamic range, there has been proposed a D/A converter of such a structure in which the capacitor 8 is charged externally during the period in which the reset switch 9 shown in FIGS. 2 and 3 is closed, i.e. during the conducting period 22 illustrated in FIG. 4 to such extent that the output level of the operational amplifier 7 of the integrator becomes lower than the ground potential level, which is followed by the integrating operation of the current(s) supplied from the constant current source 5 or sources 11 and 12. A circuit arrangement of this D/A converter is shown in FIG. 5 of the accompanying drawings, in which parts or elements equivalent to those shown in FIGS. 1 to 4 are denoted by like reference numerals. A similar circuit arrangement is disclosed in an article entitled "Bipolar LSI Technologies for Domestic Applications Aiming at Miniaturized Chip of High Speed and High Integration Density", (Nikkei Electronics, June 20, 1983 p.p. 189-193). Now referring to FIG. 5, an operational amplifier 92 has the output coupled to the inverting input of an operational amplifier 7 by way of a siwtch 91. The comparator 92 has an inverting input coupled to the output of the comparator 92 by way of a switch 92. Further, the non-inverting input terminal of the comparator 92 is connected to a junction between serially connected resistors 93 and 94, the other end of the resistor 93 being coupled to a reference voltage source V.sub.REF, while the other end of the resistor 94 is connected to the output terminal of the operational amplifier 7. A capacitor 8 is inserted between the inverting input and the output terminals of the operational amplifier 7, as in the case of the D/A converters shown in FIGS. 2 and 3. In operation, it is assumed that the voltage appearing at the output terminal 10 of the integrator is of a positive value during a period corresponding to the analogue signal output period 25 (FIG. 4). In succession to this period, the switch 91 is closed under the control of a control circuit 171 at the beginning of the period corresponding to the conducting period 22 illustrated in FIG. 4. In the initial phase of this period, the voltage applied to the non-inverting input of the operational amplifier 92 is a positive voltage the value of which is determined in accordance with the positive reference voltage V.sub.REF, the positive output voltage at the output terminal 10 of the integrator and the resistance ratio of the resistors 93 and 94. On the other hand, since the inverting input of the operational amplifier 7 is controlled to be the non-inverting input level thereof, i.e. the ground potential level, the inverting input of the operational amplifier 92 is also at the ground level. Consequently, in the initial phase of this period, a large potential difference makes appearance across the input of the operational amplifier 92, resulting in that the operational amplifier 92 supplies a large current to the capacitor 8 by way of the switch 91 to charge the capacitor 8 at an increased rate, whereby the voltage at the output terminal 10 of the integrator drops rapidly to a negative level. The D/A converter of this type suffers, however, a drawback mentioned below.
Because the capacitor 8 is abruptly supplied with electric charge during the reset period, i.e. the period in which the switch 91 is in the closed state, the instantaneous current becomes excessively large during the reset period particularly when the capacitor 8 is of a great capacity, making thus it difficult to implement the circuit in an IC (integrated circuit) configuration.
Since the amplitude of the analogue signal representing the change in the output voltage of the integrator is equal to a value derived by dividing the product of the currrent values of the constant current sources and the integration time by the value of capacity of the capacitor 8, the constant current value can not be determined independent of the value of the capacitor 8 in the circuit design.
Further, due to parasitic capacitance of the switches 13 and 14, delay will be involved in the switching operation of these switches. In order to evade such delay, limitation is imposed on the minimum current value of the constant current source 12, which thus has to be of a relatively large value. Additionally, since the maximum instantaneous current taking place during the reset period has to be restricted in consideration of the maximum permissible current of the integrated circuit, the value of the capacitor 8 must be correspondingly limited, which in turn means that the current value of the constant current source 11 is limited in dependence on the amplitude of the analogue signal. As the result, the ratio of the current value between the constant current sources 11 and 12 can not be set at freedom, to a disadvantage.
In this way, implementation of the aforementioned D/A converter mentioned above in an IC configuration has little design leeway and may be rendered impracticable in some applications.